By B. Thomas Edman, Strategy & Technology Lead, Xtremis.AI
The most powerful computer most people will ever interact with is their own brain. Eighty-six billion neurons, continuous multimodal perception, decades of real-time adaptation, all of it on roughly twenty watts of glucose. Suzana Herculano-Houzel calls it a kilogram and a half of tissue running on the equivalent of a dim lightbulb. An NVIDIA H100 draws seven hundred watts to run inference on a static model. A GB200 Superchip draws 2,700. Both the chip and the brain are computing. They are not computing the same way, and the brain’s way can be characterized in engineering terms and reproduced in silicon. The substrate the AI industry is scaling consumes four to five orders of magnitude more power than biology for cognitively narrower work, and the gap widens with each chip generation. Closing it is the next computational problem worth large amounts of capital.
The industry has so far treated this as an energy problem. GPU power per chip has tripled in three generations. A single GB200 NVL72 rack pulls roughly 130 kilowatts. Global data center electricity consumption is projected to more than double, from 415 terawatt-hours in 2024 to 945 terawatt-hours by 2030, and US data centers could reach 6.7 to 12 percent of national electricity by 2028. The buildout is without modern precedent: OpenAI’s Stargate at ten gigawatts and half a trillion dollars, xAI’s Colossus 2 standing as the first single-site cluster above one gigawatt, Meta’s Hyperion campus scaling toward five. The response has been more silicon, more cooling, more capital, in what amounts to perhaps the largest infrastructure deployment of the postwar era. But the energy problem is downstream of an architectural one. Dense matrix multiplication on synchronous hardware is a single primitive sitting at the entrance of a much deeper computational regime.
Figure 1. Power per chip across compute substrates. Operating power for representative chips and systems, grouped by substrate class and disambiguated by workload. Conventional GPUs and TPUs (red) draw 200 to 2,700 watts per chip on datacenter training and inference, and per-chip power has risen sharply across recent generations from the A100 at 400 watts to the GB200 Superchip at 2,700. Brain-inspired silicon (green) runs orders of magnitude lower on comparable workloads: IBM’s NorthPole at 74 watts for datacenter inference, Intel’s Loihi 2 and IBM’s TrueNorth at tens of milliwatts for research-scale inference. Biology (gold) anchors the comparison. The human brain operates at twenty watts on continuous multimodal cognition that exceeds the workload of any individual chip listed. Cortical Labs’ CL1 wetware system draws roughly 850 watts at the rack level because perfusion, temperature control, and life support dominate; the cellular metabolism of the neurons themselves is sub-watt.
Sources: NVIDIA datasheets (A100, H100, GB200); Google Cloud TPU v5p documentation; Modha et al., Science 381:329 (2023) [NorthPole]; Orchard et al., SiPS 2021 [Loihi 2]; Merolla et al., Science 345:668 (2014) [TrueNorth]; Cortical Labs CL1 technical specifications (March 2025); Herculano-Houzel, PLOS ONE 6:e17514 (2011) [brain reference]. GPU figures are per-chip TDP; GB200 reflects the full Grace-Blackwell Superchip. Brain-inspired figures are per-chip operating power on representative inference workloads. The human-brain reference is whole-organ metabolic consumption supporting continuous multimodal cognition, not workload-matched against any individual chip listed.
The scaling approach is already straining, and not only on power. Yann LeCun has argued for years that the largest frontier models train on fifty times less sensory data than a four-year-old takes in through the optic nerve across its first sixteen thousand waking hours. His prescription is new learning paradigms: world models, joint embedding architectures, self-supervised prediction. The critique is correct, and it stops one layer short. Convolutional networks, attention, mixture-of-experts routing, and sparse activation are refinements within a single architectural family, consisting of dense linear algebra on synchronous silicon. GPUs pipeline that algebra across thousands of cores, a real engineering achievement; TPUs and NPUs tune the same primitive into different power envelopes. Hennessy and Patterson call domain-specific accelerators the next golden age of architecture, but the AI-accelerator branch of that tree has converged on a single class of operation. Algorithmic refinement on that operation lowers training cost, but the decisive cost is inference, paid on every query for the life of the model, and that is the curve the architecture cannot fundamentally bend.
The mismatch is physical, and there is precedent for resolving this kind of mismatch. Edison’s 1879 filament made light by making heat, a resistive element glowing at roughly two percent efficiency with the rest dissipated. Current GPUs run the same kind of mismatch, brute-forcing dense matrix operations across activations that are mostly zeros and shedding the unused energy as heat. Shuji Nakamura’s blue LED did something categorically different: electrons crossing a semiconductor band gap emit photons directly which is an order of magnitude more efficient. This was not a better lamp but a different way of making light from electricity. Brain-inspired computation is the LED of thinking machines.
The brain does not perform a single trick, but rather hosts a repertoire of abilities. A handful of these mechanisms already have clean silicon analogues. Event-driven sparsity is the first: neurons stay silent until an input crosses threshold, then fire discrete spikes. In this way energy scales with information content rather than model size. Temporal coding is the second: meaning lives in the timing of spikes, not in dense activations refreshed every clock cycle. This turns time itself into a computational variable. Heterogeneous specialization is the third: the visual cortex, hippocampus, motor cortex, and cerebellum are distinct circuits with their own connectivity and dynamics. Modern dies already mix CPU, GPU, ASIC, DSP, and radio blocks for the same reason, though biology carries the principle much further. Probabilistic inference is the fourth: the brain weighs prior expectation against new evidence continuously, which is the structure of robust reasoning under uncertainty. Far from an exhaustive inventory, these are the mechanisms closest to engineering reach today, sitting near the waterline of a much larger body of computational behavior the field has barely begun to instrument.
Figure 2. The brain-inspired compute stack. Current AI engineering occupies a thin visible layer at the top of a much deeper computational stack. The transformer, the CNN, dense matmul on GPUs, and the CUDA software ecosystem are mature surface work that exploits a single computational primitive. Below the surface, six layers of brain-inspired computation are at varying stages of engineering maturity: algorithmic primitives like sparse activation and Bayesian inference that can run on existing silicon; substrate-level work in neuromorphic, photonic, in-memory, and analog AI hardware; the interconnect and memory layer where optical I/O is dissolving the von Neumann bottleneck; the orchestration layer of compilers, runtimes, and developer ecosystems that remains largely unbuilt and is the structural investable gap; frontier substrates including stochastic processing and biological wetware; and the foundational properties of biological computation that define the long-run engineering target.
Representative work and references: Pyro, TensorFlow Probability, snnTorch, Norse, Brian2 [algorithms]; IBM NorthPole (Modha et al., Science 381:329, 2023), Intel Loihi 2 (Orchard et al., SiPS 2021), BrainChip Akida, Lightmatter Envise, IBM analog AI, Mythic [substrate]; Ayar Labs, Celestial AI, NVIDIA Spectrum-X Photonics, Lumentum, Coherent [interconnect]; Intel Lava, BrainChip MetaTF, Lightmatter Idiom, Neuromorphic Intermediate Representation (Pedersen et al., Nature Communications 15:9054, 2024) [orchestration]; Vaire Computing, Cortical Labs CL1, FinalSpark, MIT Probabilistic Computing Project [frontier]. Companies and projects listed are representative, not exhaustive. Stack ordering follows substrate-to-application conventions in computer-architecture taxonomies.
What the current boom has built is real and durable. CNNs unlocked vision, transformers unlocked language, and agentic systems are unlocking autonomous execution. The GPU stack beneath them is the most valuable infrastructure shift of the past decade. However, there is a ceiling each advance presses against: inference cost, energy cost, latency, the data inefficiency LeCun points out, and the power envelope that cannot fly. Brain-inspired computation does not replace the transformer; rather, it extends its reach. Real-time multimodal inference inside a battery envelope, agentic loops that run for hours instead of seconds, always-on cognition at the edge of every sensor, vehicle, and platform: none of these are new markets bolted onto AI, but the same workloads freed from the wall they keep hitting. And the economics should compound rather than cannibalize. Drive the cost of inference down by orders of magnitude and total demand tends not to shrink; computation floods into envelopes where it was never viable before. That is the Jevons logic of efficiency revolution, and it is the mechanism by which this likely extends the incumbent instead of unseating it. This is the visible tip giving way to the body beneath it, an evolution of AI and not a lateral bet against it.
That body is also strategically contested, and the binding case for it today is defense. Consider an autonomous loitering munition. A Shahed-136-class platform carries a total electrical budget of one to two hundred watts, most of it claimed by avionics, communications, and the seeker, leaving roughly a single watt for onboard inference and no thermal headroom for active cooling. Today these munitions lean on GPS for terminal guidance, which allied electronic warfare has proven able to degrade. The capability Russian and Iranian programs are openly pursuing is terminal computer vision: a camera and processor that identify and track the target through the final approach which would make the weapon GPS-independent and robust to conventional jamming in the last kilometer. Sustained multi-camera inference inside a single-watt envelope is a substrate, interconnect, and algorithmic problem at once. Whoever fields a production version of that stack first would close a gap no GPU architecture can close at present thermal cost.
Chinese state-directed investment in this stack is neither narrowly about chips nor narrowly about drones. It spans the stack: neuromorphic substrate in Tsinghua’s Tianjic and its successors, photonic interconnect in Shanghai Jiao Tong’s optical computing initiatives, algorithmic work across the Chinese Academy of Sciences, and an outsized contribution to the open-source compiler infrastructure that will orchestrate this regime. The proliferation channel is well known. Conflict Armament Research has documented heavy Chinese-sourced electronics inside current Shahed and Geran airframes, and Treasury sanctions designations have named gray-market intermediaries shuttling components between Shenzhen and Tehran. A more capable compute payload could travel that same channel the moment the substrate is ready. The drone is the binding case because its envelope leaves no slack, but the same question runs through on-prem classified inference, persistent overhead and undersea sensing, multi-domain command and control that today resolves in seconds rather than milliseconds, and electronic-warfare signal classification that brain-inspired primitives could execute natively. The Pentagon’s FY26 autonomy line at $13.4 billion and the Replicator commitment are only the most visible procurement pull.
The primitives are properties of biological computation; the stack being built to exploit them is where capital actually enters, and the domestic version is already under construction. At the substrate layer, neuromorphic silicon implements event-driven sparsity and spike timing directly in hardware. IBM’s NorthPole chip, published in Science in October 2023, delivers twenty-five times the frames per second per watt of a GPU on the same twelve-nanometer process and even beats four-nanometer GPUs on standard inference benchmarks. Intel’s Hala Point system, deployed at Sandia in April 2024, packs 1.15 billion artificial neurons into a 2,600-watt chassis at fifteen tera-operations per second per watt. In comparison a GB200 rack achieves six on the same metric. At the interconnect layer, photonics attacks the von Neumann bottleneck with light rather than electrons, addressing data movement and computation together; Lightmatter sits at an $850 million raise and a $4.4 billion valuation, Ayar Labs at $870 million and $3.75 billion with NVIDIA, AMD, and Lockheed Martin on the cap table. At the algorithmic layer, spiking networks, probabilistic programming, and Bayesian inference are maturing as software primitives that run on the silicon already in the ground, turning probabilistic inference into a first-class operation rather than an expensive approximation; because these run on existing hardware at limited technical risk, partial integration into transformer-class workloads can yield efficiency gains with no substrate change, which makes this the nearest-term commercial play. At the frontier, biological computing remains earliest-stage, with Cortical Labs commercializing 800,000 lab-grown human neurons at $35,000 a unit, carrying the asymmetric long-horizon upside. Capital into non-GPU AI hardware exceeded five billion dollars between 2024 and 2026 across these opportunities. Yet the layer that ties them together remains to be built.
Although NVIDIA is known for its chips, its moat is the integration layer around them. CUDA shipped in November 2006. AlexNet trained on two GTX 580s and six thousand lines of CUDA in September 2012, and DOE stood up Titan at Oak Ridge the next month, putting NVIDIA silicon at the top of the TOP500. By 2025 the platform had roughly four million external developers and a moat AMD has failed to crack despite competitive silicon and a decade of trying. The durable value settled at the software layer that unified a fragmented field of chips, interconnects, and architectures into one developer surface. Brain-inspired computation is as fragmented today, scattered across neuromorphic, photonic, in-memory, analog, and biological substrates with a dozen incompatible toolchains. Intel’s Lava is open-source but Loihi 2 is not for sale; IBM’s NorthPole compiler is unreleased; BrainChip, Lightmatter, and SynSense each ship its own proprietary stack. The Neuromorphic Intermediate Representation, published in Nature Communications in September 2024, is a research interoperability layer, not a production ecosystem. Mike Davies, who runs Intel’s neuromorphic program, stated the constraint plainly in April 2024: “The neuromorphic research field does not have a neuromorphic version of the transformer.” The substrate exists well ahead of the integrator that would unify it. NVIDIA faced a similar position in 2008 and chose to build CUDA alongside the silicon. That orchestration layer compounded into an ecosystem moat that has multiplied the value of the hardware, and the enterprise built on it, ever since.
The thesis, then, is that present-day AI is the tip of an iceberg. The transformer and the GPU exploit one computational primitive among the many the brain runs on, and brain-inspired computation, taken as a stack of substrate, interconnect, algorithms, orchestration, and frontier work advancing together, opens step-changes in efficiency, capability, national-security posture, and enterprise value across the workloads where deployed AI economics will be settled. NVIDIA does not vanish from that picture. Its data center revenue for the fourth quarter of FY26 alone was $62.3 billion, and the most optimistic 2030 forecast for the entire neuromorphic chip market is about one-fifth of that single quarter. Rather than displace the incumbent, the stack opens an adjacent surface the incumbent cannot physically reach, enlarging its market on the way in by the Jevons logic above. The layers carry different entry profiles. Orchestration is where the structural gap is largest and a durable software-economics business can be built against substrate-agnostic standards. The algorithmic layer is the nearest-term revenue, deployable against existing silicon. Substrate and interconnect carry the heaviest technical risk and the most direct defense pull, and they are where Chinese state investment is concentrated. The frontier substrates hold the asymmetric long-horizon upside. A serious allocation looks less like a single-chip bet and more like a multi-layer portfolio, weighted toward where the brain’s own answer points, which is heterogeneous specialization rather than one winning circuit.
Once a dominant runtime emerges and the substrate vendors lock to it, the capital, technical, and procurement channels open today will narrow, and the firms outside the standard will pay to get in. The Council on Global Competition and Innovation – CGCI‘s frame is not patriotic capital. It is a question of which firms position now to own a piece of the dual-use compute infrastructure that stands to define economic and national-security competition for the next decade, and which wait for consensus to form and the entry price to reset. The firms that took early stakes in cloud before 2010 and in AI compute before 2020 captured most of the value those waves created. Brain-inspired computation is the next of them.
